As illustrated in FIG. 1, a .SIGMA..DELTA. digital-analog converter must be necessarily followed by a low pass filter LP SC to reconstruct the signal from the output bitstream of the .SIGMA..DELTA. demodulator of the D/A converter. There are many approaches that combine switched-capacitor techniques (SC) with continuous-time (CT) techniques. The typical approach used for implementing the low pass filter in .SIGMA..DELTA. digital-analog converters is to use a cascade of two filters. The first filter LP SC is formed with a SC technique of an order .gtoreq.2 functioning with a clock frequency f.sub.s, equal to the frequency of the output bitstream data of the .SIGMA..DELTA. demodulator.
The second filter CT is usually realized with a CT technique to eliminate the "imaging" in the vicinity of the f.sub.s frequency and, if required, to drive through the filter's last stage the chip external outputs. The second filter CT usually occupies a large area because of the large time constants that are normally realized with integrated resistors and capacitors according to the scheme shown in FIG. 1, whose spectral response diagrams are illustrated in FIGS. 1a and 1b.
In non-audio applications, where rejection of the clock frequency imaging about f.sub.s, is not required, an efficient approach is to use a "multirate" fully SC filter, that is, a filter of order .gtoreq.3 whose first stages operate with a clock frequency f.sub.s, equal to f.sub.s, whereas the last stages have a clock frequency f.sub.s, equal to f.sub.s /2.sup.n (n=1,2,3, . . . ). In this way, the last stage of the filter LP SC may function simultaneously as an off-chip buffer without excessive power consumption. Indeed, the use of an SC buffer with a clock frequency equal to f.sub.s, which is usually rather high because of the oversampled nature of the output stream of the .SIGMA..DELTA. demodulator, is prohibitive for low-power applications.
The disadvantage of this approach is that in stages with a clock frequency equal to f.sub.s /2.sup.n, the noise occurring at those frequencies is brought back into the baseband (B) via aliasing.
The .SIGMA..DELTA. D/A input node that receives a signal with a high noise energy at frequencies well above the baseband (B) of the signal to be processed in the vicinity of f.sub.s /2.sup.n causes such an energy density that aliasing of this noise in the baseband degrades the signal/noise ratio (SNR) of the reconstructing filter. This nullifies the beneficial effect of the .SIGMA..DELTA. conversion, as shown in the FIGS. 2, 2a, 2b and 2c.
Moreover, to further reduce the clock frequency and thus the power of the operational amplifiers, facilitating also the functioning of the output buffer, double sampled SC structures are often used. These structures are typically realized by duplicating each switched-capacitor and by inverting the associated control phases. However, this realization may introduce a further aliasing error equal to the mismatch among the input capacitances of alternate phases of the first input stage.